Electronic devices include many different integrated circuits corresponding to different data paths, where each data path extends between a respective input node and a respective output node. A given data path within an integrated circuit that has the maximum delay between receipt of a signal at its input node and generation of a signal at its output node is referred to as a critical path of the integrated circuit. There can be many critical paths in a given integrated circuit.
A static timing analysis (STA) tool is used to identify critical paths within the integrated circuit through simulated operation of the integrated circuit. The STA tool can also determine a maximum clock frequency at which the integrated circuit can operate given the signal delay characteristics of the critical path(s) of the integrated circuit. However, because the STA tool relies upon simulation of the integrated circuit operation, various assumptions that affect timing performance of the integrated circuit must be made in modeling the integrated circuit in the STA tool. These assumptions are often made in a conservative manner with respect to determining the maximum clock frequency at which the integrated circuit can successfully operate. For example, the STA tool can apply many margins on various parameters such as fabrication process variation, operating temperature, operating voltage, among others. Therefore, the as-fabricated integrated circuit often performs better than the integrated circuit as simulated in the STA tool. Thus, the maximum clock frequency determined by the STA tool may include excess margin.
Due to the margin in the STA analysis, it may be possible to operate the as-fabricated integrated circuit at a higher clock frequency that the maximum clock frequency determined by the STA tool. However, if the clock frequency of the real-world integrated circuit is increased too much, the circuit can operate incorrectly. It is within this context that the present invention arises.